-- Listado del detector de flancos
library ieee;
use ieee.std_logic_1164.all;

entity edge_detect is
   port(
      clk, reset: in std_logic;
      level: in std_logic;
      posedge: out std_logic;
      negedge: out std_logic
   );
end edge_detect;


architecture GateLevel of edge_detect is
    signal Reg : STD_LOGIC_VECTOR (2 downto 0);
begin
  process  -- shiftreg
  begin
    wait until CLK'event and CLK='1';
    if reset='1' then Reg <= (others=>'0');
      else Reg <= Level & Reg(2 downto 1); end if;
  end process;
  -- combinational logic
  -- posedge <= '1' when Reg(1 downto)="10" else '0';
  posedge <= Reg(1) and (not Reg(0));
  negedge <= Reg(0) and (not Reg(1));
end GateLevel;

--Edge_inst :entity edge_detect
--  port map (
--    clk	    => ,
--    reset   => ,
--    level   => , --input
--    posedge => , --output
--    negedge =>   --output
--  );
